Presenter: Moritz Brunion, Universität Bremen

Inviting Professor: Prof. Dr. Alberto Garcia Ortiz

Abstract: 

Over the last decades, digital systems have improved their power, performance and functional density generation over generation. Since several nodes the geometrical scaling of the transistor is becoming increasingly harder. Thus, while geometrical device scaling still has some options left, more will be needed to satisfy the growing demand for energy-efficient compute resources. To still push the limits further, the arrangement of the transistor has evolved from bulk to finFET and now GAAFET. In addition to these transformations, co-optimizing the technology definition targets with other layers and domains in the design stack was able to substantially support the effective functional density scaling.

But eventually, the gain of these mechanisms will be exhausted, and a different solution will the required to avoid technology becoming stagnant. For that, there could be completely different devices with new switching mechanisms, like carbon nanotube, or the deposition of new materials with 2D-properties. But as part of the process development for more immediate CMOS-based technologies features, the concept of backside power distribution and fine-grain 3D stacking have shown to be feasible, and are approaching an increasing level of maturity. These two capabilities combined allow to connect stacked devices at the granularity of standard-cells, which could allow to lift a fundamental constraint of CMOS scaling until now: Finding the single, scalable device that can do everything the digital system requires well. This presentation will give an overview on the exploration landscape, with some examples of some initial experiments towards understanding the interactions of different technology choices. Further, EDA challenges in the domain of physical design are identified and potential solutions are described.