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Future memory technology and memory organisation options for NVM-based memory hierarchy in low power processor platforms

Organizer: Eingeladen durch Prof. Dr. Alberto Garcia Ortiz
Location: NW1, H3
Start Time: 02. December 2021, 16:00
End Time: 02. December 2021, 18:00


Prof. Francky Catthoor, IMEC Leuven


Scaling of volatile SRAM and DRAM memories is hitting limits on read and write power, area and endurance/reliability characteristics. For that reason, several researchers have started to study alternatives based on embedded non-volatile memory (eNVM) options. The currently available STT-MRAMs and other resistive RAMS are very promising in terms of reducing leakage and area, and indirectly also the dynamic read power. But they are not meeting the write and read speed requirements and partly also endurance/reliability is still a serious challenge.

Hence the also other emerging memory options are being explored which have the promise to improve on read/write latency and endurance, while maintaining the energy advantage. But concurrently also the memory organisation has to be revisited and they have to be co-optimized. In this talk a few interesting directions will be highlighted, including the link to the overall exploration framework.

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